700.305 (14S) Chip Design 1
Overview
- Lecturer
- Course title german Chip Design 1
- Type Lecture - Colloquia (continuous assessment course )
- Hours per Week 2.0
- ECTS credits 4.0
- Registrations 6 (25 max.)
- Organisational unit
- Language of instruction Englisch
- Course begins on 01.03.2014
Time and place
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Course Information
Teaching methodology including the use of eLearning tools
Vorlesung, Übungen mit CAD WerkzeugenCourse content
Topics
- Grundlagen des IC-Entwurfs, Eigenschaften digitaler Schaltungen
- pn-Übergänge (Dioden) und MOS Transistoren
- Spice Modelle und Masken-Design-Regeln
- Verdrahtung, Parameter und Modelle
- Inverter, Ratioed- und Komplementärlogik (CMOS), Schaltverzögerung
- Leistungsaufnahme von CMOS Schaltungen
- Statische kombinatorische Logik in CMOS
- Statische sequentielle Logik in CMOS
- Kategorien integrierter Schaltungen - "Full Custom", zellbasiert und arraybasiert (FPGA)
- Designhierarchien, VHDL und Logiksynthese
Teaching objective
Überblick zum Thema "Integrierten Schaltungen"Prior knowledge expected
Elektronik Grundkenntnisse (Bauelemente, Schaltungsentwurf, Modellierung)Other materials
Kopie der Vorlesungsfolien, ÜbungsunterlagenLiterature
Jan Rabaey, Digital Integrated Circuits, A Design PerspectiveTeaching methodology including the use of eLearning tools
Lectures, labs using CAD toolsCourse content
Topics
- Basics in IC-Design, properties of digital circuits
- pn-junction (diode) and MOS transistors
- Spice models and mask design rules
- interconnect, parameters and models
- Inverter, ratioed and complementary logic (CMOS), propagation delay
- Power consumption
- Static combinatorial logic in CMOS
- Static sequential logic in CMOS
- Integrated Circuits by category, full custom, cell based and array based (FPGA)
- Design hierarchies, VHDL und logic synthesis
Teaching objective
Introduction to integrated circuitsPrior knowledge expected
Fundamentals in electronic engineering (components, circuit design and modelling)Other materials
Copies of lectures slides, task descriptions for labsLiterature
Jan Rabaey, Digital Integrated Circuits, A Design PerspectiveExamination information
Im Fall von online durchgeführten Prüfungen sind die Standards zu beachten, die die technischen Geräte der Studierenden erfüllen müssen, um an diesen Prüfungen teilnehmen zu können.
Assessment criteria / Standards of assessment for examinations
Schriftliche Prüfung
Assessment criteria / Standards of assessment for examinations
Written examGrading scheme
Grade / Grade grading schemePosition in the curriculum
- Master's degree programme Information Technology
(SKZ: 489, Version: 06W.3)
-
Subject: Additional Technical Module II
(Compulsory subject)
-
3.1-3.3 Lecture with Exercises or Lecture with Seminar (
6.0h VK/VS / 12.0 ECTS)
- 700.305 Chip Design 1 (2.0h VK / 4.0 ECTS)
-
3.1-3.3 Lecture with Exercises or Lecture with Seminar (
6.0h VK/VS / 12.0 ECTS)
-
Subject: Additional Technical Module II
(Compulsory subject)
Equivalent courses for counting the examination attempts
-
Sommersemester 2024
- 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
-
Sommersemester 2023
- 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
-
Sommersemester 2022
- 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
-
Sommersemester 2021
- 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
-
Sommersemester 2020
- 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
-
Wintersemester 2018/19
- 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
-
Wintersemester 2016/17
- 700.305 VC Chip Design (2.0h / 4.0ECTS)
-
Sommersemester 2015
- 700.305 VK Chip Design 1 (2.0h / 4.0ECTS)
-
Sommersemester 2013
- 700.305 VK Chip Design 1 (2.0h / 4.0ECTS)