700.305 (22S) Chip Design 1

Sommersemester 2022

Registration deadline has expired.

First course session
23.03.2022 08:15 - 12:00 Online Off Campus
... no further dates known

Overview

Due to the COVID-19 pandemic, it may be necessary to make changes to courses and examinations at short notice (e.g. cancellation of attendance-based courses and switching to online examinations).

For further information regarding teaching on campus, please visit: https://www.aau.at/en/corona.
Lecturer
Course title german Chip Design 1
Type Lecture - Course (continuous assessment course )
Course model Online course
Hours per Week 2.0
ECTS credits 4.0
Registrations 7 (25 max.)
Organisational unit
Language of instruction Englisch
Course begins on 23.03.2022
eLearning Go to Moodle course

Time and place

Please note that the currently displayed dates may be subject to change due to COVID-19 measures.
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Course Information

Intended learning outcomes

The course should provide a detailed introduction to chip design including devices, modeling, design, simulation and layout of integrated circuits.

Teaching methodology including the use of eLearning tools

Lectures and labs using CAD tools

Course content

  • Basics in integrated circuits (chip) design
  • Properties of digital and analog integrated circuits
  • Basic solid-state physics and models of pn-junction diodes and MOS transistors
  • Introduction to IC technology / process and mask layout
  • Design and analysis of basic transistor circuits like switches, currentmirrors, amplifiers
  • Basics of OPAMP design
  • Static combinatorial and sequential logic in CMOS (optional)
  • Labs and homework

Prior knowledge expected

Fundamentals in electronic devices and circuits

Literature

Lectures slides and lab descriptions  will be provided during lecture.

Recommended literature for deeper studies:

  • Behzad Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, Inc. 2001.
  • Jan Rabaey, Digital Integrated Circuits, A Design Perspective


Examination information

Im Fall von online durchgeführten Prüfungen sind die Standards zu beachten, die die technischen Geräte der Studierenden erfüllen müssen, um an diesen Prüfungen teilnehmen zu können.

Grading scheme

Grade / Grade grading scheme

Position in the curriculum

  • Master's degree programme Information and Communications Engineering (ICE) (SKZ: 488, Version: 15W.1)
    • Subject: Information and Communications Engineering: Supplements (NC, ASR) (Compulsory elective)
      • Wahl aus dem LV-Katalog (Anhang 4) ( 0.0h VK, VO, KU / 14.0 ECTS)
        • 700.305 Chip Design 1 (2.0h VC / 4.0 ECTS)
  • Master's degree programme Information and Communications Engineering (ICE) (SKZ: 488, Version: 15W.1)
    • Subject: Information and Communications Engineering: Supplements (NC, ASR) (Compulsory elective)
      • Wahl aus dem LV-Katalog (Anhang 4) ( 0.0h VK, VO, KU / 14.0 ECTS)
        • 700.305 Chip Design 1 (2.0h VC / 4.0 ECTS)

Equivalent courses for counting the examination attempts

Sommersemester 2024
  • 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
Sommersemester 2023
  • 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
Sommersemester 2021
  • 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
Sommersemester 2020
  • 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
Wintersemester 2018/19
  • 700.305 VC Chip Design 1 (2.0h / 4.0ECTS)
Wintersemester 2016/17
  • 700.305 VC Chip Design (2.0h / 4.0ECTS)
Sommersemester 2015
  • 700.305 VK Chip Design 1 (2.0h / 4.0ECTS)
Sommersemester 2014
  • 700.305 VK Chip Design 1 (2.0h / 4.0ECTS)
Sommersemester 2013
  • 700.305 VK Chip Design 1 (2.0h / 4.0ECTS)